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Ç¥ÁعøÈ£ TTAK.OT-10.0288 ±¸Ç¥ÁعøÈ£
Á¦°³Á¤ÀÏ 2010-12-23 ÃÑÆäÀÌÁö 0
ÇѱÛÇ¥ÁØ¸í ½Ã½ºÅÛ ¼öÁØ ¹ÝµµÃ¼ IP ÀÎÅÍÆäÀ̽º ¸ðµ¨¸µ
¿µ¹®Ç¥Áظí System-Level Semiconductor IP Interface Modeling
Çѱ۳»¿ë¿ä¾à º» Ç¥ÁØÀº ½Ã½ºÅÛ ¼öÁØ¿¡¼­ ¹ÝµµÃ¼ IP ÀÎÅÍÆäÀ̽º¸¦ ±â¼úÇϱâ À§ÇÏ¿© Level 0, Level 1, Level 2, Level 3ÀÇ 4°¡Áö ±¸Ã¼µµ ¼öÁØÀ» Á¤ÀÇÇÏ¸ç °¢°¢ÀÇ ±¸Ã¼µµ ¼öÁØ¿¡ µû¶ó ±â¼úÇÏ¿©¾ß ÇÏ´Â µ¥ÀÌÅÍ È帧, ºí·Ï, Æ÷Æ®, ½ÅÈ£, ¸ðµ¨¸µ ÆÄÀÏ, ±â¼ú ¾ð¾î¸¦ ¸í½ÃÇÑ´Ù.
¿µ¹®³»¿ë¿ä¾à This standard defines 4 levels of abstractions, i.e. level 0, level 1, level 2, and level 3, to describe semiconductor IP interfaces in system level. It also specifies data flows, blocks, ports, signals, modeling files, and description languages according to levels of abstraction.
±¹Á¦Ç¥ÁØ VSIA (VSI Alliance), "System-Level Interface Behavioral Documentation Standard (SLD) 1 1.0", 2000
°ü·ÃÆÄÀÏ TTAK.OT-10.0288.zip TTAK.OT-10.0288.zip            

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