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Ç¥ÁØÁ¾·ù | Á¤º¸Åë½Å´ÜüǥÁØ(TTAS) | ||||||||||||||||
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Ç¥ÁعøÈ£ | TTAE.IE-802.3cx-2023 | ±¸ Ç¥ÁعøÈ£ | |||||||||||||||
Á¦°³Á¤ÀÏ | 2024-12-06 | ÃÑ ÆäÀÌÁö | 87 | ||||||||||||||
ÇÑ±Û Ç¥Áظí | IEEE ÀÌ´õ³Ý Ç¥ÁØ °³Á¤ 6: °³¼±µÈ Á¤¹Ð ½Ã°£ ÇÁ·ÎÅäÄÝ(PTP) ŸÀÓ ½ºÅÆÇÎ Á¤È®µµ¸¦ Áö¿øÇϱâ À§ÇÑ ¸Åü Á¢±Ù Á¦¾î(MAC) ¼ºñ½º ÀÎÅÍÆäÀ̽º¿Í °ü¸® ¸Å°³º¯¼ö (IEEE Std 802.3cx-2023) | ||||||||||||||||
¿µ¹® Ç¥Áظí | IEEE Standard for Ethernet Amendment 6: Media Access Control (MAC) Service Interface and Management Parameters to Support Improved Precision Time Protocol (PTP) Timestamping Accuracy (IEEE Std 802.3cx-2023) | ||||||||||||||||
ÇÑ±Û ³»¿ë¿ä¾à | ÀÌ Ç¥ÁØÀº Á¤¹Ð ½Ã°£ ÇÁ·ÎÅäÄÝÀÇ Å¸ÀÓ ½ºÅÆÇÎ Á¤È®µµ¸¦ ¼ºê-³ª³ëÃʱîÁö Áö¿øÇϱâ À§ÇØ IEEE Std 802.3-2022 Ç¥ÁØÀÇ 30, 45, 90ÀýÀ» ¼öÁ¤Çϰí, ºÎ¼Ó¼ 90A¸¦ Ãß°¡ÇÑ °ÍÀÌ´Ù. 30.2Ç׿¡¼ TimeSync °ü¸® °´Ã¼¿¡ ¼ºê-³ª³ëÃÊ °´Ã¼¸¦ Ãß°¡ÇÏ¿´À¸¸ç, 45.2Ç׿¡¼´Â Á¤È®ÇÑ ÃÖ´ë/ÃÖ¼Ò ¼Û½Å/¼ö½Å °æ·Î µ¥ÀÌÅÍ Áö¿¬ ½Ã°£À» ÃøÁ¤Çϱâ À§ÇÏ¿© PHY °èÃþÀÇ PMA/PMD, WIS, PCS, PHY XS, DTE XS, TC ·¹Áö½ºÅÍ¿¡ ¼ºê-³ª³ëÃʸ¦ Ãß°¡ÇÏ¿© ³ª³ëÃÊ¿Í ¼ºê-³ª³ëÃÊ·Î ±¸ºÐÇÏ¿´´Ù. 90 Ç׿¡¼´Â ´Ù¾çÇÑ ½Ã°£ µ¿±âÈ ÇÁ·ÎÅäÄÝÀ» Áö¿øÇϱâ À§ÇØ µ¥ÀÌÅÍ Áö¿¬ ÃøÁ¤ À§Ä¡¸¦ ÇØ´ç Ç¥ÁØ¿¡ µû¶ó 2°¡Áö À§Ä¡·Î ±¸ºÐÇÏ¿© Á¤È®ÇÑ ÀÔ/Ãâ·Â ½Ã°£ ÃøÁ¤ÀÌ °¡´ÉÇϵµ·Ï ÇÏ¿´À¸¸ç, Á¤·Ä ¸¶Ä¿/ÄÚµå¿öµå ¸¶Ä¿/¾ÆÀ̵éÀÇ »ðÀÔ/Á¦°Å, ´ÙÁß PCS ·¹Àο¡ ÀÇÇÑ ºÐ¹è/º´ÇÕÀ¸·Î ¹ß»ýµÇ´Â ½ºÅ¥·Î ÀÎÇØ µ¿Àû °æ·Î µ¥ÀÌÅÍ Áö¿¬ Á¤º¸¸¦ Á¦°øÇÏ¿© ³ôÀº Á¤È®µµÀÇ °æ·Î µ¥ÀÌÅÍ Áö¿¬ ½Ã°£À» ÃßÁ¤ÇÒ ¼ö ÀÖµµ·Ï ÇÏ¿´´Ù. ºÎ¼Ó¼ 90A¿¡¼´Â ŸÀÓ ½ºÅÆÇÁ Á¤È®µµ¿¡ ¿µÇâÀ» ÁÖ´Â ´ÙÁß PCS ·¹Àΰú Á¤·Ä ¸¶Ä¿/ÄÚµå¿öµå ¸¶Ä¿/¾ÆÀ̵éÀÇ »ðÀÔ/Á¦°Å, ´ÙÁß ·¹ÀÎ PHY¿¡¼ ¹ß»ýµÇ´Â ½ºÅ¥ µîÀ» °í·ÁÇÏ¿´´Ù. | ||||||||||||||||
¿µ¹® ³»¿ë¿ä¾à | This standard is intended to support the time stamping accuracy of precision time protocols up to sub-nanoseconds in the IEEE Std 802.3-2022 standard. In Clause 30.2, a sub-nanosecond object was added to the TimeSink management object, and in Clause 45.2, sub-nanoseconds were added to the PMA/PMD, WIS, PCS, PHY XS, DTE XS, and TC registers of the PHY layer to measure the exact max/min transmit/receive path data delay time, divided into nanoseconds and sub-nanoseconds. In Clause 90, In order to support various time synchronization protocols, the data delay measurement location was divided into two locations according to the applicable standard to enable accurate measurement of input/output time, and due to skew caused by insertion/removal of alignment markers/codeword markers/idle, distribution/merging by multiple PCS lanes, dynamic path data delay information was provided so that high accuracy path data delay time could be estimated. Annex 90A considered multiple PCS lane and alignment markers/codeword marker/idle and skew generated by multiple lane PHY that affect timestamp accuracy. | ||||||||||||||||
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