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| Ç¥ÁØÁ¾·ù | Á¤º¸Åë½Å±â¼úº¸°í¼(TTAR) | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Ç¥ÁعøÈ£ | TTAR-10.0063 | ±¸ Ç¥ÁعøÈ£ | |||||||||||||||
| Á¦°³Á¤ÀÏ | 2016-11-03 | ÃÑ ÆäÀÌÁö | 0 | ||||||||||||||
| ÇÑ±Û Ç¥Áظí | °íÀå °¨³» ·¹º§0 ij½Ã Á¦¾î±â ÀÎÅÍÆäÀ̽º (±â¼úº¸°í¼) | ||||||||||||||||
| ¿µ¹® Ç¥Áظí | Fault Tolerant L0 Cache Controller Interface (Technical Report) | ||||||||||||||||
| ÇÑ±Û ³»¿ë¿ä¾à | ÀÌ ±â¼úº¸°í¼´Â ij½ÃÀÇ µ¥ÀÌÅ͸¦ º¸È£Çϱâ À§ÇØ ·¹º§ 1,2 ij½Ã ¿Ü¿¡ ·¹º§ 0 ij½Ã¸¦ ±¸ºñÇÏ°Ô µÇ°í ·¹º§ 0 ij½Ã¸¦ ÅëÇØ ÇÁ·Î¼¼¼¿¡ ÀÇÇÑ °íÀåÀ» °¨ÁöÇϰí ÀÌ·¯ÇÑ °íÀå¿¡ ÀÇÇØ ¿À¿°µÈ µ¥ÀÌÅͰ¡ ÁÖ ¸Þ¸ð¸®¿¡ ¹Ý¿µµÇÁö ¾Êµµ·Ï Çϴ ij½Ã Á¦¾î±â ±¸Á¶¸¦ Á¦½ÃÇÏ°í °íÀå °¨³» ij½Ã¸¦ Á¦¾îÇϱâ À§ÇÑ ÀÎÅÍÆäÀ̽º¸¦ Á¦½ÃÇϰí ÀÖ´Ù. | ||||||||||||||||
| ¿µ¹® ³»¿ë¿ä¾à | This report suggests using an interface, comprised of the level 0 cache and the level 1 and level 2 cache, to control the fault detector in the fault tolerant cache controller and a fault tolerant level 0 cache controller architecture in order to detect the fault of the processor. | ||||||||||||||||
| °ü·Ã IPR È®¾à¼ | Á¢¼öµÈ IPR È®¾à¼ ¾øÀ½ | ||||||||||||||||
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