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¿µ¹® Ç¥Áظí Multichip-based artificial intelligence processor software interface (Technical Report)
ÇÑ±Û ³»¿ë¿ä¾à °Å´ë Àΰø½Å°æ¸ÁÀ» ±¸ÇöÇϰųª Àΰø½Å°æ¸ÁÀÇ ¼º´ÉÀ» °³¼±Çϱâ À§ÇØ ÀΰøÁö´É ÇÁ·Î¼¼¼­¸¦ ´ÙÁß Ä¨ ±¸Á¶·Î ¼³°èÇÏ¿© ¸ðµ¨ º´·ÄÈ­ ¶Ç´Â µ¥ÀÌÅÍ º´·ÄÈ­ ±â¹ýÀ» Àû¿ëÇÒ ¼ö ÀÖ´Ù. ÀÌ ±â¼úº¸°í¼­´Â ´ÙÁß Ä¨ ±â¹ÝÀÇ ÀΰøÁö´É ÇÁ·Î¼¼¼­ ±¸Á¶¸¦ Ȱ¿ëÇÒ ¼ö ÀÖ´Â ¼ÒÇÁÆ®¿þ¾î ±Ô°ÝÀ» ·¹Áö½ºÅÍ ·¹º§¿¡¼­ Á¤ÀÇÇϰí, Á¤ÀÇÇÑ ·¹Áö½ºÅ͸¦ Á¦¾îÇϱâ À§ÇÑ API ÀÎÅÍÆäÀ̽º ¹× ÀΰøÁö´É ¾Ë°í¸®ÁòÀ» ÇÁ·Î¼¼¼­¿¡¼­ ¼öÇàÇϱâ À§ÇÑ µ¿ÀÛ ¿¹µµ ÇÔ²² ¼³¸íÇÑ´Ù.
¿µ¹® ³»¿ë¿ä¾à The technical report defines an software interface specification that can utilize multi-chip based artificial intelligence processor structure to apply model parallelism or data parallelism to artificial intelligence processor for the implementation of large artificial neural network or the acceleration of artificial neural network, API interface for controlling defined register and an operation example for performing artificial intelligence algorithm in the processor will be described.
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