Ȩ > ÀڷḶ´ç > ÀÚ·á°Ë»ö > Ç¥ÁØ
ÀÚ·á °Ë»ö°á°ú
Ç¥ÁØÁ¾·ù | Á¤º¸Åë½Å´ÜüǥÁØ(TTAS) | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Ç¥ÁعøÈ£ | TTAK.OT-10.0306 | ±¸ Ç¥ÁعøÈ£ | |||||||||||||||
Á¦°³Á¤ÀÏ | 2011-09-28 | ÃÑ ÆäÀÌÁö | 78 | ||||||||||||||
ÇÑ±Û Ç¥Áظí | È¥¼º ½ÅÈ£ ȸ·Î¸¦ À§ÇÑ Å×½ºÆ® ·ÎÁ÷ | ||||||||||||||||
¿µ¹® Ç¥Áظí | Test Logic for Mixed-Signal Circuit | ||||||||||||||||
ÇÑ±Û ³»¿ë¿ä¾à | º» Ç¥ÁØÀº È¥¼º ½ÅÈ£ ȸ·ÎÀÇ Å×½ºÆ® ·ÎÁ÷ ¹× ±× ±¸¼º ¿ä¼Ò¸¦ Å×½ºÆ® ·ÎÁ÷ ¾ÆÅ°ÅØÃÄ,
TAP, TAP Á¦¾î±â »óÅÂ, TAP Á¦¾î±â µ¿ÀÛ, ATAP, ·¹Áö½ºÅÍ ±¸Á¶, ¸í·É¾î ·¹Áö½ºÅÍ, Å×½º Æ® µ¥ÀÌÅÍ ·¹Áö½ºÅÍ, ¹ÙÀÌÆÐ½º ·¹Áö½ºÅÍ, ¹Ù¿î´õ¸® ½ºÄµ ·¹Áö½ºÅÍ, ¸í·É¾î, Çʼö ¸í·É¾î, ±ÇÀå ¸í·É¾î, ¼±Åà ¸í·É¾î, TBIC, DBM, ABMÀÇ 17°³ Ç׸ñÀ¸·Î ³ª´©¾î ±ÔÁ¤ÇÑ´Ù. |
||||||||||||||||
¿µ¹® ³»¿ë¿ä¾à |
This standard specifies the test logic and its elements of mixed- signal circuits
with 17 parts, i.e. test logic architecture, TAP, TAP controller states, TAP controller operations, ATAP, register architecture, instruction register, test data register, bypass register, boundary- scan register, instructions, mandatory instructions, recommended instructions, optional instructions, TBIC, DBM, and ABM. |
||||||||||||||||
°ü·Ã IPR È®¾à¼ | Á¢¼öµÈ IPR È®¾à¼ ¾øÀ½ | ||||||||||||||||
°ü·ÃÆÄÀÏ |
![]() |
||||||||||||||||
Ç¥ÁØÀÌ·Â |
|
||||||||||||||||
Ç¥ÁØÀ¯Áöº¸¼öÀÌ·Â |
|