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Ç¥ÁعøÈ£ TTAK.OT-10.0288/R1 ±¸Ç¥ÁعøÈ£
Á¦°³Á¤ÀÏ 2014-12-17 ÃÑÆäÀÌÁö 22
ÇѱÛÇ¥ÁØ¸í ½Ã½ºÅÛ ¼öÁØ ¹ÝµµÃ¼ IP ÀÎÅÍÆäÀ̽º ¸ðµ¨¸µ
¿µ¹®Ç¥Áظí System-Level Semiconductor IP Interface Modeling
Çѱ۳»¿ë¿ä¾à º» Ç¥ÁØÀº ½Ã½ºÅÛ ¼öÁØ¿¡¼­ ¹ÝµµÃ¼ IP ÀÎÅÍÆäÀ̽º¸¦ ±â¼úÇϱâ À§ÇÏ¿© ¼öÁØ CO, ¼öÁØ PO, ¼öÁØ SN, ¼öÁØ SI, ¼öÁØ IMÀÇ 5°¡Áö ±¸Ã¼µµ ¼öÁØÀ» Á¤ÀÇÇÏ¸ç °¢°¢ÀÇ ±¸Ã¼µµ ¼öÁØ¿¡ µû¶ó ±â¼úÇÏ¿©¾ß ÇÏ´Â µ¥ÀÌÅÍ È帧, ºí·Ï, Æ÷Æ®, ½ÅÈ£, ¸ðµ¨¸µ ÆÄÀÏ, ±â¼ú ¾ð¾î¸¦ ¸í½ÃÇÑ´Ù.
¿µ¹®³»¿ë¿ä¾à This standard defines 5 levels of abstractions (level CO, level PO, level SN, level SI, and level IM) to describe semiconductor IP interfaces in system level. It also specifies data flows, blocks, ports, signals, modeling files, and description languages according to levels of abstraction.
±¹Á¦Ç¥ÁØ VSIA SLD 1 1.0
°ü·ÃÆÄÀÏ TTAK.OT-10.0288_R1_[1].pdf TTAK.OT-10.0288_R1_[1].pdf            

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