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¿µ¹®Ç¥Áظí Extended Instruction Set Computer Architecture of Microprocessor
Çѱ۳»¿ë¿ä¾à º» Ç¥ÁØÀº ¸¶ÀÌÅ©·ÎÇÁ·Î¼¼¼­ÀÇ È®Àå ¸í·É¾î ÁýÇÕ(EISC, Extended Instruction Set Computer) ±¸Á¶¸¦ ±ÔÁ¤Çϸç, ·¹Áö½ºÅÍ ±¸Á¶¿Í ¸í·É¾îÀÇ È®Àå ¹æ¹ýÀ¸·Î ±¸¼ºµÇ¾î ÀÖ´Ù. ¸í·É¾îÀÇ È®Àå ¹æ¹ý¿¡¼­´Â ¿ÀÇÁ¼Â °ªÀÇ È®Àå, Áï½Ã(immediate)°ªÀÇ È®Àå, ºÐ±â(¡®Branch¡¯) ¸í·É¾îÀÇ È®Àå, ±âŸ ¸í·É¾îÀÇ È®ÀåÀ» ´Ù·é´Ù.
¿µ¹®³»¿ë¿ä¾à This standard specifies the Extended Instruction Set Computer (EISC) architecture of a microprocessor. It can extend its instructions to process some instructions those cannot be handled by the Reduced Instruction Set Computer (RISC) with fixed instruction length. This standard consists of register architecture and extension method of instructions.
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