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Ç¥ÁعøÈ£ | TTAK.KO-09.0047/R2 | ±¸Ç¥ÁعøÈ£ | |||||||||
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Á¦°³Á¤ÀÏ | 2012-10-09 | ÃÑÆäÀÌÁö | 32 | ||||||||
ÇѱÛÇ¥Áظí | Çϵå¿þ¾î±â¼ú¾ð¾î ÄÚµù Áöħ | ||||||||||
¿µ¹®Ç¥Áظí | Hardware Description Language Coding Guidelines | ||||||||||
Çѱ۳»¿ë¿ä¾à | º» Ç¥ÁØÀº Verilog HDL°ú VHDLÀÇ µÎ HDL ¾ð¾î¿¡¼ ÅëÀÏµÈ ÄÚµù ¹æ¹ýÀ» À§ÇÑ ÄÚµù ÁöħÀ¸·Î ±¸¼ºµÇ¾î ÀÖÀ¸¸ç, °¢ HDL ¾ð¾î¿¡¼ Á¦½ÃÇÏ´Â ÄÚµù ÁöħÀº ÆÄÀÏÇì´õ, °¡µ¶¼º ÄÚµù, ÀÌÀü¿ëÀ̼ºÀ» À§ÇÑ ÄÚµù, Ŭ·Ï°ú ¸®¼ÂÀ» À§ÇÑ Áöħ, ¹ö½º Áöħ, ÇÕ¼º ÄÚµùÀÇ 6°³ ÀåÀ¸·Î ±¸¼ºµÇ¾î ÀÖ´Ù. | ||||||||||
¿µ¹®³»¿ë¿ä¾à | This standard consists of coding guidelines of Verilog HDL and VHDL for unified and well-organized coding methods. Verilog HDL and VHDL guidelines consist of 6 chapters of File Header, Coding for Readability, Coding for Portability, Guidelines for Clocks and Resets, Guidelines for Buses, and Coding for Synthesis. | ||||||||||
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°ü·ÃÆÄÀÏ | TTAK_KO-09_0047R2.pdf | ||||||||||
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