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¿µ¹®Ç¥Áظí Processor with structure of exended instruction set computer
Çѱ۳»¿ë¿ä¾à º¹ÇÕ ¸í·É¾î(CISC:Complex Instruction Set Computer) ´Â °¡º¯ ±æÀÌÀÇ ¸í·É¾î ±¸Á¶·Î ¾î¶°ÇÑ ±æÀÌÀÇ ¿ÀÆÛ·£µåµµ Ç¥Çö ÇÒ ¼ö ÀÖ¾î ÄÚµå ¹Ðµµ°¡ ³ôÀº ÀåÁ¡À» °¡Áö¸ç, Ãà¾à ¸í·É¾î(RISC: Reduced Instruction Set Computer)´Â °íÁ¤ ±æÀÌ ¸í·É¾î¸¦ »ç¿ëÇϱ⠶§¹®¿¡ ¸í·É¾î º¹È£±â(Decoder) ȸ·Î°¡ °£´ÜÇÏ°í ¿¹¿Ü 󸮰¡ ¼Õ½¬¿öÁ® ÆÄÀÌÇÁ¶óÀÎ ¹× ¸Þ¸ð¸® °ü¸® ÀåÄ¡°¡ °£ÆíÇØÁö´Â ÀåÁ¡ÀÌ ÀÖ´Ù. º» È®Àå ¸í·É¾î(EISC: Extended Instruction Set Computer)´Â ±âº»ÀûÀ¸·Î Çϵå¿þ¾î°¡ °£´ÜÇÑ RISC ±¸Á¶À̸鼭 16ºñÆ® °íÁ¤µÈ ¸í·É¾î¿Í È®Àå °¡´ÉÇÑ CISC ±¸Á¶·Î ³ôÀº ¼º´ÉÀ» º¸À̵µ·Ï ÇÏ¿´À¸¸ç ÄÚµå ¹Ðµµ ¶ÇÇÑ CISCÀÇ 20%, RISCÀÇ 40% Á¤µµ·Î Çö°ÝÇÏ°Ô ³ôÀº ÀåÁ¡À» °¡Áö°í ÀÖÀ¸¸ç, ¸Þ¸ð¸® µ¿ÀÛÀ» Çö°ÝÇÏ°Ô ÁÙÀÓÀ¸·Î½á, ÀúÀü·Â, °í¼º´É¿¡ ÀûÇÕÇÑ ¸¶ÀÌÅ©·ÎÇÁ·Î¼¼¼­ÀÌ´Ù.
¿µ¹®³»¿ë¿ä¾à This standard consists of EISC structure that is RISC structure of fixed 16 bit instruction and CISC structure of extendable. So, this structure is able to operate high performance, and low power, and low code density that is 40% less than CISC and 20% less than RISC.
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IMT-2000 3GPP - Åë½Å °ü¸®; Å×½ºÆ® °ü¸® ÅëÇÕ ÂüÁ¶Á¡(IRP); Corba ¼Ö·ç¼Ç ¼¼Æ® (R9)
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IMT-2000 3GPP - Åë½Å °ü¸®; Å×½ºÆ® °ü¸® ÅëÇÕ ÂüÁ¶Á¡(IRP); SOAP ¼Ö·ç¼Ç ¼¼Æ®(SS) (R9)