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Ç¥ÁØÁ¾·ù | Á¤º¸Åë½Å´ÜüǥÁØ(TTAS) | ||||||||||||||||
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Ç¥ÁعøÈ£ | TTAK.KO-10.0960 | ±¸ Ç¥ÁعøÈ£ | |||||||||||||||
Á¦°³Á¤ÀÏ | 2016-12-27 | ÃÑ ÆäÀÌÁö | 15 | ||||||||||||||
ÇÑ±Û Ç¥Áظí | ºñµð¿À º´·Ä󸮸¦ À§ÇѺñµð¿À ´ÜÀ§ (ŸÀÏ) Á¤º¸ ½Ã±×³Î¸µ | ||||||||||||||||
¿µ¹® Ç¥Áظí | Video Unit (Tile) Information Signaling for Video Parallel Processing | ||||||||||||||||
ÇÑ±Û ³»¿ë¿ä¾à | ÀÌ Ç¥ÁØÀº °íÈ¿À² ºñµð¿À ºÎÈ£È Å¸ÀÏ(Tile)°ú °°Àº ºñµð¿À ´ÜÀ§ °ü·Ã Á¤º¸¸¦ ½Ã±×³Î¸µÇÏ´Â ±â¼úÀ» ´ã°í ÀÖÀ¸¸ç, ±â¼úÀÇ ÀåÁ¡À» ¼³¸íÇϱâ À§ÇØ (1) ºñµð¿À Ç¥ÁØÀÇ º´·ÄÈ µµ±¸ ¼³¸í(¿¹: °íÈ¿À² ºñµð¿À ºÎÈ£È Å¸ÀÏ ±â¼ú), (2) º» Ç¥ÁØÀ» (ºñ)´ëĪ CPU ÄÚ¾î ±â¼ú¿¡ Á¢¸ñÇÏ¿´À» °æ¿ì ±â´ëµÇ´Â ¼º´ÉÇâ»óÀ» ¼³¸íÇÑ´Ù. ±×¸®°í, (3) Á¦¾ÈÇϴ ǥÁØ ½Ã±×³Î¸µ ±Ô°Ý (±¸¹® (½ÅÅØ½º), Àǹ̷Ð(½Ã¸àƽ½º))À» ±â¼úÇÑ´Ù. | ||||||||||||||||
¿µ¹® ³»¿ë¿ä¾à | The standard includes the specifications for video unit (e.g. tile) signaling such as HEVC Tile. It consists of three sections: (1) video parallel processing tool such as HEVC Tile, (2) two expecting performance gains from applying the standard to (a)symmetric CPU multi-cores, and (3) the standard signaling specifications including syntax and semantics. | ||||||||||||||||
°ü·Ã IPR È®¾à¼ | Á¢¼öµÈ IPR È®¾à¼ ¾øÀ½ | ||||||||||||||||
°ü·ÃÆÄÀÏ |
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