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¿µ¹® Ç¥Áظí SW Platform for Safety-critical Distributed System with Multi-core Processors – Part 4 : Reference Model for Symmetric Multiprocessing Scheduler (Technical Report)
ÇÑ±Û ³»¿ë¿ä¾à º» ±â¼úº¸°í¼­´Â ´ÙÁß ÄÚ¾î ÇÁ·Î¼¼¼­¸¦ Áö¿øÇϱâ À§ÇÑ ½Ç½Ã°£ ¿î¿µÃ¼Á¦ÀÇ ½ºÄÉÁÙ·¯ ±â¼úÀÇ ÂüÁ¶ ¸ðµ¨À» Á¦¾ÈÇÑ´Ù. ÇØ´ç ±â¼úÀº ´ÙÁß Äھ Áö¿øÇϱâ À§ÇÑ ÄÚ¾î ÀνÄ, ij½Ã Àϰü¼º À¯Áö, °øÀ¯ ÀÚ¿ø °ü¸® µîÀÇ Çʼö ¿ä¼Ò ±â¼ú°ú ARINC 653 ±â¹Ý ÆÄƼ¼Ç ¿î¿µÃ¼Á¦ÀÇ ÆÄƼ¼Ç ¹× ÇÁ·Î¼¼½º¸¦ ´ÙÁß Äھ ÇÒ´çÇÏ´Â ½ºÄÉÁÙ·¯ ±â¼úÀÇ ÀýÂ÷¸¦ Æ÷ÇÔÇÑ´Ù.
¿µ¹® ³»¿ë¿ä¾à The technical report proposes a reference model for multi-core scheduler which is a component of real-time operating system which consists distributed SW platform. This technology includes primitive techniques supporting multi-cores and scheduler mechanism for partition and process. Primitive technique includes procedure for booting secondary core, TLB configuration for cache consistency, spinlock for shared data structure. Scheduler mechanism includes a procedure for selecting partition and process and allocating it to multi-cores.
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°ü·ÃÆÄÀÏ    TTAR-11.0050.pdf TTAR-11.0050.pdf
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